v11.0 [Sep 21, 2011]
- New performance monitoring capabilities in the external memory interface toolkit improve productivity by helping designers achieve maximum memory efficiency. By tracking and reporting the efficiency of the memory system in real time, designers can find the optimal settings by exploring different memory controller settings. Designers can also use the monitoring capabilities to help optimize their traffic patterns. The performance monitoring capabilities complement existing features of the external memory interface toolkit to help designers calibrate, optimize, and debug their memories.
- The Transceiver Toolkit delivers an improved channel manager interface and updated transceiver control panel. The channel manager interface now provides real-time status on links and channels (transmitters and receivers) enabling designers to quickly identify which links are passing or failing. The updated transceiver control panel enables users to simultaneously view the status and edit the settings of both channels of a link (transmitter and receiver) while displaying more transceiver status information compared to previous versions. These enhancements to the Transceiver Toolkit enable designers to help optimize their transceivers for improved signal integrity and bring their boards up faster.
- Enhanced Chip Planner – Provides improved usability when designing and verifying Stratix V FPGA transceivers. The more detailed and intuitive layout enables designers to better manage their transceiver resources
- Expanded operating system (OS) support for DSP Builder – Added support for 64-bit Windows and Linux
- Newly available IP cores – Deinterlacer II IP core
- Quartus II software version 11.0 offers support for expanded transceiver modes and features for Stratix V FPGAs
- Additional Device Support
